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Date Added: YESTERDAY

Fpga Design Engineer

Enfield Town, EN2, UK
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Company: COPELLO

Job Type: Contract, Full Time

Salary: £70 - £80/hour

Copello are seeking an experienced FPGA Design Engineer to join a high-technology engineering team on a 6-month contract based in North London. This role will play a key part in the design, debugging, and implementation of VHDL-based FPGA solutions for complex electronic systems, with a strong focus on RADAR and DSP applications.

Key Responsibilities

* Design, debug, and implement VHDL for FPGA-based systems

* Develop and maintain VHDL test benches and test vectors to verify FPGA functionality

* Define and analyse requirements from component level through to full system level

* Decompose high-level system requirements into implementable FPGA designs

* Work on systems containing multiple FPGAs and ensure correct system integration

* Use laboratory test equipment such as spectrum analysers, signal processors, and related tools to validate designs

* Conduct formal design reviews and contribute to technical decision-making

* Produce clear, concise technical documentation throughout the development lifecycle

* Ensure designs are delivered on time and within budget constraints

Required Experience & Skills

* Proven experience in FPGA design using VHDL

* Strong background working on multi-FPGA systems

* Experience analysing high-level system requirements and translating them into detailed designs

* Hands-on experience with lab test equipment (e.g. spectrum analysers, signal processors)

* Experience in RADAR and/or DSP applications

* Ability to produce robust, well-documented designs under time and budget pressures

* Experience conducting and participating in design reviews

Desirable

* Experience working in safety-critical or high-reliability environments

* Familiarity with full product development lifecycles

This role will require candidates to have active SC or eligibility for SC. Role is 4 days a week onsite in North London.

Position is paying £70 -£80 per hour
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