Sr. level Engineering SoC / ASIC chip design contract (18 month). You will be utilizing the latest techniques working on a radiation hardened chip for space vehicles. The Position is open to those that have expertise in the following areas.
1. Development of Chiplet SoC DV environment (tools, flows / methodologies, testbenches, emulation)
2. Development of Chiplet Verification Cross-Reference Matrix (VCRM) - mapping all Chiplet requirements to tests / testbenches
3. Multiple block-level and/or subsystem-level DV tasks, including RTL simulation, formal verification, and potentially HW/SW co-sim
4. Chiplet-level simulation / emulation tasks
Qualifications: >12 years experience with ASIC/SoC design / verification and >5 years leading ASIC/SoC design verification (DV) teams. Expertise in modern DV tools, languages, and methodologies, including System Verilog, UVM, UPF. Experience with hardware/software co-simulation is desired but not required
We cover liability and professional liability insurance throughout your contract.
Will contracted through Boeing for through NASA contract.
Role: Senior ASIC Design Engineer
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