Join a multi-national Physical Design team as a Snr VLSI & SoC Physical Design Engineer contributing to the development of state-of-the-art Satellite SoCs, from design to production. Work on chips with complex digital and analog modules, including next-generation radiation-hardened satellite modems, using leading-edge EDA tools and process technologies.

Key Responsibilities:

* Physical implementation of complex SoCs and VLSI devices, integrating custom and 3rd-party IP.

* Full block-level timing closure and manufacturing checks, including power planning and analysis.

* Collaborate with Logic Design RTL team to develop timing constraints at block and chip level.

* Insert DFT test structures and support chip-level integration, capture, and simulation.

* Contribute to process improvements and career development initiatives.

Experience:

* BSc in Electrical Engineering, Computer Science, or related field.

* Strong commercial experience in physical design engineering (ASIC/SoC).

* Deep knowledge of COT/ASIC design flows: synthesis, floor-planning, P&R, CTS, STA, timing closure, physical verification, power analysis, DFT/ATPG.

* Experience with deep sub-micron processes (28nm or below).

* Proficiency in scripting languages (Tcl, Python, Perl) and EDA tools (Cadence or Synopsys).

* Strong problem-solving, analytical, and collaboration skills.

* Experience interfacing with design teams, IP/library suppliers, and EDA vendors.

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