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DATE ADDED: Mon 27/01/2020

Design Verification Engineer

Menlo Park, CA, US


JOB TYPE: Permanent, FullTime

Responsibilities: Write and augment existing testplans.Implement testbench and scoreboards / checkers.Implement test sequences as per plan and debug failures. Achieve 100% functional and code coverage. Work closely with designers, micro architects & f/w to resolve issues. Ability to communicate & articulate clearly progress / issues with project leads Required Skills: 5 years of proven experience as a DV engineer Hands on experience with SV and UVM Hands on Experience with executable test plans and Coverage Driven verification Hands on Experience with Synopsys VCS / Verdi or Cadence Incisive tools Familiarity with C/C++BSEE/CS or equivalent experience Desired Skills: Python (or similar) scripting language ASIC design experience Experience in Computer Graphics or Compression is desirable MSEE/CS or equivalent experience - provided by Dice