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Date Added: Fri 28/05/2021

Formal Verification Engineer

San Jose, CA, US
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Job Type: Permanent, FullTime

Minimum Qualifications bull BSEEMSEEBSCompEMSCompE with 5 years of industry experience bull 3+ years of System Verilog HVL and hands-on experience on Verilog or VHDL bull Deep understanding of design development with reasonable complexity bull Deep understanding of testplan, coverage and verification strategies bull 3+ years of experience in Formal Verification and tools related to formal like Magellan, Jasper, IFV etc. bull Familiarity with Python3BashTcl scripting is a must bull Experience with debugging simulation failures to guide digital design bull Experience of tapout of at least one complex SoC with Formal Verification Job Duties bull Develop verification strategy for complex SoC, decide partition of verification for dynamic simulation and formal verification bull Develop testplan for Formal Verification of chip and IPs bull Work with Design team to decide on IP partitioning bull Verify IPSoC with Formal verification and Dynamic Simulation and close verification bull Develop infrastructure for formal verification using PerlPythonShellTCL scripting bull Provide detailed verification report to project manager eInfochips is an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, gender, sexual orientation, gender identity, national origin, veteran or disability status
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